The present invention generally relates to semiconductor devices and more particularly to a testing method and testing apparatus of semiconductor integrated circuit devices.
A semiconductor integrated circuit device generally includes therein a large number of semiconductor devices each constituting a gate. Thus, manufacturers of semiconductor integrated circuit devices are required to conduct a thorough test before shipment of the semiconductor integrated circuit devices as a product.
While the test of such semiconductor integrated circuit devices includes testing of electrical properties of the individual element devices, functional test is becoming more important recently particularly in relation to high-performance semiconductor integrated circuit devices performing versatile functions.
In the functional test of semiconductor integrated circuit devices, a wafer or chip formed with semiconductor integrated circuit device to be tested is mounted upon a test bed of a testing apparatus called an LSI tester, and a test vector is produced and supplied to the semiconductor integrated circuit device, wherein the test vector is a combination of input signal pulses formed by pattern generators in correspondence to various operational states of the semiconductor integrated circuit device.
Thus, the testing apparatus is provided with a power supply unit that drives the semiconductor integrated circuit device to be tested, and the semiconductor integrated circuit device under testing performs operations corresponding to the test vectors. Thereby, the operation of the semiconductor integrated circuit device is measured by a measuring device connected to an output pin.
FIG. 1 schematically shows the construction of a conventional testing apparatus 10 used commonly for testing semiconductor integrated circuit devices.
Referring to FIG. 1, the testing apparatus 10 includes a test bed 11 formed of a probe card, wherein the test bed 11 is mounted with a semiconductor integrated circuit device 11A to be tested. Further, the testing apparatus 10 includes a power supply unit 12 supplying a driving current to the semiconductor integrated circuit device 11A mounted upon the test bed 11, and a measurement unit 13 is provided for measuring the electrical properties of the semiconductor integrated circuit device 11A thus mounted upon the test bed 11.
In the illustrated example, the measuring unit 13 includes an UDC (universal DC) unit 13A and an MDC (multiple DC) unit 13B used for measuring the dc characteristics.
Further, the testing apparatus 10 is provided with pattern generators such as an ALPG (algorithmic pattern generator) 14A having the function of internal operation and producing the test bit patterns, an SCPG (scan pattern generator) 14B generating and storing scan patterns necessary for realizing LSSD (level-sensitive scan design), and the like, wherein the pin data constituting the test vector is formed from the test bit patterns thus produced by various pattern generators by a pin data selector 15A, which is provided also as a part of the testing apparatus 10.
The pulses constituting the pin data thus formed are then supplied to the semiconductor integrated circuit device 11A on the test bed 11 via a wave formatter 11A, wherein the wave formatter 11A is provided as a part of the testing apparatus.
Further, the testing apparatus 10 is provided with a rate generator 15B that determines the test period by generating a system clock and controls the foregoing wave formatter 15A via a timing generator 16B by way of the system clock thus generated.
Further, the testing apparatus 10 is provided with an SQPG (sequential pattern generator) 16C that stores the test pattern in a buffer memory and produces the test pattern by outputting the content of the buffer memory at high speed. Thereby, the SQPG 16C controls the timing generator 16B via the timing memory 16C and further the wave formatter 16A via a wave memory.
Further, the testing apparatus 10 is provided with a TTB (truth table buffer) 16D, which is a field for storing the test pattern in the pattern generator, wherein the TTB 16D controls the timing generator 16B via the timing memory 16C and the wave formatter 16A via the wave memory.
Further, the response of the semiconductor integrated circuit device 11A to the foregoing test vector is sent to a digital comparator 16E for comparison, and the result of the comparison is stored in a data fail memory 15E and an AFM (address fail memory) 15F.
Further, the testing apparatus 10 includes a processor 10A that controls the operation of various parts of the testing apparatus 10.